Dr. Kaushik Roy
Professor
Dr. Jay Shah
India Site Lead
Dr. David Rogers
Founder & Director
Shivraj Gurpadappa Dharne
India Site Lead
Prof. Hidenori Mimura
Director
Vinayak Bharat Naik
MRAM Device Lead
Dr. Arindam Sanyal
Professor
Sripad Sheshagiri Nagarad
India Site Lead
Dr. Daniel Moraru
Associate Professor
Dr. Prabha Sundaravadivel
Assistant Professor
Dr. Amey Kulkarni
Deep Learning Engineer
About
Vellore Institute
of Technology
VIT was established in the year 1984 as Vellore Engineering College by Dr.G.Viswanathan, Founder & Chancellor. The institute was upgraded as a university in recognition of its academic excellence in 2001 by the Ministry of Human Resources Development, Government of India. VIT today comprises of twelve constituent schools and interdisciplinary centers offering 24 undergraduate, 30 postgraduate and research programs up to Ph.D. level. With the aim of providing quality higher education at par with international standards, VIT persistently seeks and adopts innovative methods in teaching and learning. The university has students from all corners of the globe, nurtured by learned and experienced faculty. VIT has signed Memoranda of Understanding for the exchange of students and faculty, research collaborations and consultancy activities with various international universities, research organisations and industries. VIT University is the first Indian institute to get international accreditation from IET, UK, and NAAC, India. All B.Tech programmes at VIT are accredited by the Engineering Accreditation Commission of ABET, USA. VIT is also ranked as No.1 private engineering institute by MHRD (NIRF-2016 ranking).
ICMDCS 2021
The 2nd International Conference on Microelectronic Devices, Circuits and Systems (ICMDCS 2021) will be held at the Vellore Institute of Technology (VIT), Vellore India from 11th to 13th February 2021. The conference covers the subject areas including: digital IC design, analog/RF/Mixed Signal IC design, Device Modeling and Technology, RF communication circuits, embedded systems; nonlinear circuits and system In addition to the technical papers, the conference also covers tutorials on recent advancements in the above said areas, Keynote and Plenary sessions by leading industry leaders and renowned academicians. It is planned to publish the peer reviewed and selected papers of conference as proceedings with Springer in their prestigious Communications in Computer and Information Science series.
Speakers
Dr. Kaushik Roy
Professor
Electrical and Computer Engineering
Purdue University,
West Lafayette, Indiana
Dr. Jay Shah
India Site Lead
Fab Engineering
GLOBALFOUNDRIES, India
Dr. David Rogers
Founder & Director
Nanovation, France
Shivraj Gurpadappa Dharne
India Site Lead
Technology Enablement
GLOBALFOUNDRIES, India
Prof. Hidenori Mimura
Director
Research Institute of Electronics
Shizuoka University, Japan
Vinayak Bharat Naik
MRAM Device Lead
GLOBALFOUNDRIES, Singapore
Dr. Arindam Sanyal
Dept. of Electrical Engineering,
University of Buffalo, USA
Sripad Sheshagiri Nagarad
India Site Lead
Pre & Post Fab Operations
GLOBALFOUNDRIES, India
Dr. Daniel Moraru
Associate professor
Dept. of Electeronics and Materials Science
Shizuoka University, Japan
Dr. Prabha Sundaravadivel
Assistant Professor
Electrical Engineering
The University of Texas, USA
Dr. Amey Kulkarni
Deep Learning Engineer
NVIDIA
San Jose, California, USA
Tutorial
Session-1
Mr. Praveen Paul is currently working as RF & Analog Mixed Signal Compact Modeling Engineer with Globalfoundries. He completed his Masters from IIT Madras in Microelectronics & VLSI Design. His areas of interest are the modeling and characterization of passive devices like Resistors, Capacitors, Diodes and Varactors for RF and Analog applications.
Mr. Varuna AB AB received M.Tech. degree from IIT Kanpur, India. He is currently with the Design Enablement group, Globalfoundries, Bangalore, India. His current research interests include the design, optimization and implementation of RF and millimeter-wave integrated circuits using high-performance inductors, capacitors and transformers.
Session-2
Mr. Padmanaban Kalyanaraman has a post graduate degree in Applied Electronics from Anna University, Chennai. He has 14+ years of experience in digital design for both FPGA and ASIC
Padmanaban is FPGA University Outreach Program Specialist at Intel’s Programmable solutions Group. Prior to Joining Intel, he served as a Chief Faculty at Sandeepani School of Embedded System design (CoreEL Technologies, Bangalore) and as an Assistant Professor and Project Coordinator at MSRUAS, Bangalore.
Session-3
Mr. Jai Sehgalis a Corporate Application Engineer at Siemens EDA business. He has been working in DFT role with expertise in Tessent Fastscan, Testkompress and ScanPro products. He is a gold medallist and scholarship holder graduated from Amity University, Noida. Apart from that he has published and presented 5 research papers in national and international conferences related to VLSI, Signal processing, Artificial intelligence and Embedded system domains. Currently he is working on test solutions and supporting Tessent DFT products covering scan, compression, ATPG, JTAG, iJTAG and BIST. In his leisure time he enjoy cooking and playing cricket.
Session-4
Mr.Pavan Kumar Nanduri is working as Senior Application Engineer for HyperLynx products in Mentor Graphics. Pavan is having a cumulative experience of 12+ years across Industry and Academia. Pavan has rich demonstrated working experience in the areas of Signal & Power Integrity, Electromagnetic Compatibility & Electromagnetic Interference (EMI EMC), RF Design and Electromagnetics and was a part of product development. His areas of Interests are High Speed Digital Signal Design and its challenges related to SI, PI and Conducted/Radiated Emissions. In his free time Pavan likes to spend time reading literature, listening Carnatic music and watching movies.
Call for Papers
Digital Design (Track-1)
Logic and physical synthesis, physical design, timing and signal integrity, power integrity, design for manufacturability, design for yield, design challenges for advanced technology nodes, low-power design, power-aware and energy-efficient design, thermal management, battery-aware design, energy harvesting, CAD Tools, Verification methodologies, DFT, fault modeling and simulation, ATPG, BIST, board-level and system-level test, memory test.
Analog, Mixed- Signal and RF Design: (Track-2)
Design of analog, mixed-signal, and RF IP, high-speed wired and wireless communication interfaces, low-power analog and RF, memory design, standard cell design.
Technology and Devices: (Track-3)
Advanced Logic and Memory devices, Flexible and Organic Electronics, Photovoltaics and Energy Systems, Nano-electro-mechanical Systems and Sensors, Optoelectronics and Photonics, Compound Semiconductor Devices, Computational Modeling at the Nanoscale, Semiconductor Materials and Processes, Emerging Materials and Devices, Device Reliability.
System-level Design: (Track-4)
System-level design methodologies, processor and memory design, multicore systems, GPU design, on-chip communication architectures and networks-on-chip, performance analysis, defect-tolerant architectures, machine learning), : Hardware/Software co-design, embedded SoC, embedded multi-core systems, board-level hardware, hardware platforms for Internet-of-Things (IoT) devices, Reconfigurable computing, FPGA architecture and FPGA circuit design, CAD for FPGA, FPGA prototyping, FPGA-based accelerators for cloud servers, Wireless sensor networks, low-power wireless systems, wireless protocols, wireless power delivery.
Emerging Technologies: (Track-5)
MEMS, CMOS sensors, design methodologies for nanotechnology, post-CMOS devices, biomedical circuits, carbon nanotube-based computing, spintronics, silicon photonics, neuromorphic computing.
Important Dates
Please make a note!
Full Paper Submission
Click here to Submit your PaperNotification of Acceptance
Camera Ready paper
Registration(Conference & Tutorial)
Gallery
Check our gallery from the ICMDCS – 2017
Industrial Partners
Committees
Steering Committee
- Dr.G.Viswanathan, Chancellor, VIT (Patron)
- Dr. Sankar Viswanathan, Vice-President, VIT (Co-Patron)
- Dr. Sekar Viswanathan, Vice-President, VIT (Co-Patron)
- Dr. G.V.Selvam , Vice- President, VIT (Co-Patron)
- Ms. Kadhambari S. Viswanathan, Assistant Vice - President, VIT (Co-Patron)
- Dr. Rambabu Kodali, Vice-Chancellor, VIT (Co-Patron)
- Dr.S.Narayanan, Pro Vice-Chancellor, VIT (Co-Patron)
Technical Program Committee
- Mr. Aditya Deulkar, Samsung Semiconductor India R & D, Bangalore
- Dr. Abhishek Ramanujam, Analog Devices ,Ireland
- Dr.Xiao-Zhi Gao, Helsinki University of Technology, Finland
- Dr.Roy Paily, Indian Institute of Technology, Guwahati, India
- Dr.Parameswaran Ramanathan, Wisconsin-Madison University, USA
- Dr.Vignesh Rajamani, Vice President, IEEE Electromagnetic Compatibility Society, Oakland University, USA
- Dr.Navin Bishnoi, Marvel Semiconductors, Bengaluru, India
- Dr.Sreehari Veeramachaneni, BITS, Hydrabad, India
- Dr.Debesh K Das, Jadavpur University, Kolkata, India
- Dr.Maryam Shojaei Baghini, Indian Institute of Technology, Bombay, India
- Dr.P.Krishnamoorthi, Philips India Pvt. Ltd, Bengaluru, India
- Dr.P.Sakthivel, Anna University, Chennai, India
- Dr.P.Ramesh, Amritha University, Kolkata, India
- Dr.G.Lakshminarayanan, National Institute of Technology, Trichy, India
- Dr .Sakthivel P, Anna University, Chennai, India
- Dr.Sang Hyeon Kim, Korea Advanced Institute of Science and Technology, South Korea
- Mr. Sudarshan Srinivasan, R&D Intel, Bengaluru, India
- Dr. Tapan K Nayak, CERN, Geneva
- Dr. Vanathi P T, PSG College of Technology,Coimbatore,India
- Dr. Venkata Vanukuru, Global Foundries, Bengaluru, India
- Dr. Venkateswaran N, SSN College of Engg, Chennai, India
- Dr.Virendra Singh, IIT Bombay, India
- Dr. Vita Pi-Ho Hu,National Chiao Tung University, Taiwan
- Dr. Xingsheng Wang, University of Glasgow, Glasgow, Scotland
- Dr. Anis Suhaila Mohd Zain, Technical University of Malaysia , Malacca, Malaysia
- Mr. Ashok Govindarajan, Zilogic Systems, Chennai
- Mr. Balamurugan G, Honeywell, Bangalore
- Dr. Chandrasekar,Colorado State University,USA
- Dr. Changhwan Shin,Sungkyunkwan University, Seoul, South Korea
- Dr. Chi On Chui ,University of California, Los Angeles
- Dr. Hyungcheol Shin, Seoul National University, South Korea
- Dr.Jawahar Senthilkumar V, Anna University, Chennai, India
- Mr. Gaurav Goel, Intel, Bangalore
- Mr. Jayaraman K,Maxim Integrated, Bangalore
- Dr. Jing Guo, University of Florida, USA
- Dr. Jongwook Jeon, Konkuk University, Seoul
- Dr.Yang Hao, Queen Mary University of London, UK
- Dr.Lakshminarayanan,NIT, Trichy, India
- Mr. Lavakumar A, Synopsys, Bangalore
- Dr. Meganathan D, Anna University, Chennai, India
- Dr. Moorthi S, NIT, Trichy, India
- Dr.Nirmal kumar P, Anna University, Chennai, India
- Mr. Pradeep Nair,Texas Instruments, India, Bangalore
- Dr. N. Balamurugan , Thiagarajar College of Engineering, Madurai, India
- Dr.C.P.Ravikumar, Texas Instruments, Bengaluru
- Dr.Vipin Madangarli, Global Foundries, Bengaluru,India
- Dr. G. Seetharaman, National Institute of Technology, Nagaland,India
- Dr. M Raja, BITS, Pilani, Dubai Campus, UAE
- Dr. Kewal K Saluja, University of Winsconsin-Madison, Madison WI
- Dr. Krishnendu Chakrabarty, Duke University, Durham,NC
- Dr. Xiao-Zhi Ga, Helsinki University of Technology, Finland
- Dr. Subramaniam Ganesan, Oakland University Rochester, MI
- Dr. Anand Paul, Kyungpook National Univeristy, South Korea
- Dr. K. Bharanitharan, Tainan, Taiwan
- Dr. Vijaya Sankara Rao Pasupureddi, Carinthia University of Applied Sciences, Austria
- Dr. Vishwani D.Agrawal, Samuel Ginn College of Engineering, Auburn University,
- Mr.Balamurugan G, Honeywell, Bangalore
- Dr. V. Kamakoti, Indian Institute of Technology Madras, India
- Dr. Susmita Sur-Kolay, ACM Unit, Indian Statistical Institute, India
- Dr. M. Sabarimalai Manikandan, IIT, Bhuvaneshwar ,India
Organizing Committee
- General Chairs: Dr. Kittur Harish Mallikarjun, Dean, SENSE
- Organising Chairs: Dr. V.Arunachalam , Dept. of Micro and Nano Electronics,
SENSE
Dr. K.Sivasankaran, Dept. of Micro and Nano Electronics, SENSE - Technical Session Chairs: Dr. S.Sivanantham, Dept. of Micro and Nano Electronics,
SENSE
Dr. R. Saktivel, Dept. of Micro and Nano Electronics, SENSE - Tutorial Chair: Dr. Kumarvel, Dept. of Micro and Nano Electronics, SENSE
- Technical Review Chair: Dr. V. Nitish Kumar, Dept. of Micro and Nano Electronics, SENSE
- Registration Chairs: Dr. Sri Abibhatla Sridevi, Dept. of Micro and Nano Electronics,
SENSE
Dr. V. N. Ramakrishnan, Dept. of Micro and Nano Electronics, SENSE
Prof. M Aarthy, Dept. of Micro and Nano Electronics, SENSE - Finance Chair: Prof. P. Jayakrishnan, Dept. of Micro and Nano Electronics, SENSE
- Website Chair: Prof. C Prayline Rajabai, Dept. of Micro and Nano Electronics, SENSE
- Hospitality Chairs: Dr. T. Pradeep, Dept. of Micro and Nano Electronics, SENSE
Prof. K. Jagannadha Naidu, Dept. of Micro and Nano Electronics, SENSE
Prof. G. Raghunath, Dept. of Micro and Nano Electronics, SENSE - Publicity Chairs: Prof. S Ravi, Dept. of Micro and Nano Electronics, SENSE
Prof. R Dhanabal, Dept. of Micro and Nano Electronics, SENSE - Sponsorship Chairs: Prof. Rajeev Pankaj N, Dept. of Micro and Nano Electronics,
SENSE
Prof. Satheesh Kumar S, Dept. of Micro and Nano Electronics, SENSE
Conference Registration
| Registration - (Faculty / Student / Research Scholar / Industry) | ||
| Indian Authors | Foreign Authors | |
| Conference | Rs.1000 | USD 15 |
| Tutorial | Rs.250 / Track | - |
| Conference and Tutorial | Rs.1250 | - |
*If more than one author of an accepted paper wishes to attend the conference, all such authors need to register separately as an author.
Each accepted paper must be registered by paying Rs.1000
Contact Us
Organising Chair
Dr.V.Arunachalam
Dr. K.Sivasankaran