| SI No. | Paper Title | Author | Name of the Institute |
|---|---|---|---|
| 1 | Innovative Approaches to Implementing Logic Gates with Memristors: A Comprehensive Study on Circuit Design and Performance | Bhaskara Rao Jammu, Venkata Sridevi Pulakandam, Naya Nandini Singampalli, Yukthi Sri Raghava Bomma, Sandhya Elapanda, Navya Deepthi Chintada, Sairam Dola | Gayatri Vidya Parishad College of Engineering(Autonomous) |
| 2 | Development of Nanomaterial based Microfluidic Point of Care Testing Device | Manasi Avadhoot Mahajan, Manisha R, Reena Monica P | VIT Chennai |
| 3 | Performance Analysis of Intercalation doped Multilayer Graphene Nanoribbons for on Chip Interconnect Applications | Ganesh Patil, Aparna Kalpande | VNIT Nagpur |
| 4 | Automating Schematic Driven Layout Generation with Pin Creation and Placement for Optimizing Workflows and Maximizing Efficiency | Parv Malhotra, Neha Agrawal, Garima Batra, Hitesh Marwah | Cadence Design Systems |
| 5 | Increase Productivity with Automatic Pin Generation for hierarchical Layouts | Garima Batra, Neha Agrawal, Hitesh Marwah | Cadence Design Systems |
| 6 | A Novel Mixed Signal IP Packaging Solution for SoC Verification | Lalit Mohan, Vijay Akkaraju, Priyanshi Rastogi | Cadence Design Systems |
| 7 | Advanced Low Power Simulation with Liberty and UPF | Chethan G Kumar, Arumugan A | Cadence Design Systems |
| 8 | Cadence Cerebrus: An intelligent Chip Explorer for Physical Design flow | Chandra Sekhar Kanuru, Harshini A, Rajanikant Sakariya, Yusuf Ghadiali | Texas Instruments |
| 9 | Formal Assurance of Connectivity and Data Integrity for efficient IP verification | Gulshan Kumar Sharma, Sougata Bhattacharjee, Avinash Bollu, Akshaya Jain | Samsung Semiconductor India Research |
| 10 | Planning Ahead For End-to-end Formal Complexity | Ankit Saxena, Radheshyam Baviskar, Shubhangi Goel | Marvell Technology |
| 11 | Practical application of Advance Fault models | Pervez Garg, Piyushkumar M Chaniyara | Texas Instruments |
| 12 | Neuromorphic Architectures | Devi Sanjana M, Abhinav A, Devarsi K M, Nitishwaran V, Boopase Kumar C | SNS College Of Technology |
| 13 | Double MAC based Block Matrix Multiplication for Neural Network on FPGA | Aparna Nair M K, Boggavarapu Sravani, Kala S, Nalesh S | IIIT Kottayam |
| 14 | Design and Simulation of Class-E Power Amplifier for 13.56 MHz Near Field Communication Technology Applications | Ganesh Racha, K Lal Kishore, Yedukondalu Kamatham, P Srinivasa Rao | CVR College of Engineering |
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