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| 8.00 AM to 9.30 AM | Registration | |||||||||||||||||||||||||||||||||||
| 9.30 AM to 10.45 AM | Inauguration Chief Guest Hitesh Garg, Vice President & India Managing Director, NXP Semiconductors Visionary Keynote Speaker Sridhar Vembu, Co-Founder & CEO, Zoho Corporation Guest of Honor Satya Gupta, President, VLSI Society of India Venue: Anna Auditorium |
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| 10.45 AM to 11.30 AM | High Tea Venue: CS Hall |
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| 11.30 AM to 12.15 PM | Keynote-1: Transforming Cloud Infrastructure for the AI era (Navin Bishnoi, Country Head - Marvell) Venue: Anna Auditorium |
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| 12.15 PM to 1.00 PM | Keynote-2: 3D-IC design Integration and Test Challenges (Srijesh Parambath, Sr. Manager, (Siemens EDA) Venue: Anna Auditorium |
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| 1.00 PM to 1.45 PM | Networking Lunch Venue: Foodys |
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| 1.45 PM to 2.15 PM | Keynote-3: AI-Driven Test for Optimized DFT and Enhanced Silicon Health (Shamitha Rao - Sr. Manager, Solutions Group, Synopsys,India) Venue: Anna Auditorium |
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| 2.15 PM to 2.45 PM | Keynote-4 : Semiconductors - A brief overview (Alok Kuchlous, CEO, Mirafra Technology) Venue: Anna Auditorium |
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| 2.45 PM to 3.45 PM | Poster Presentation, PhD Research Forum Venue: CS Hall |
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| 2.45 PM to 3.45 PM | Networking Break Venue: CS Hall |
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| 3.45 PM to 5:15 PM | Technical Session 1 | |||||||||||||||||||||||||||||||||||
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| 5:30 PM to 6:30 PM | Panel Discussion | |||||||||||||||||||||||||||||||||||
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Topic: Electronics & Semiconductors - New Era of Opportunities |
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| 6:30 PM to 7:30 PM | Cultural Program Venue: Anna Auditorium |
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| 7:30 PM Onwards | Networking Dinner Venue: Anna Auditorium Basketball Court |
| TIME | EVENT DETAILS | ||||||||||||||||||||||||||||||||||||||||
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| 8.00 AM to 9.30 AM | Registration Venue: CS Hall |
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| 9.30 AM to 10.00 AM | Invited Talk 1: EV - Inside out & EV as the emerging market for India Product ECO System (Nachiket Hardas, Director, Renesas Electronics India Private Limited) Venue: Anna Auditorium |
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| 10.00 AM to 10.30 AM | Keynote-5 : Minimal Fab New Generation of Semiconductor Manufacturing - Introductive Presentation, (Mickael Lozac'h, Business Development Manager, Yokogawa Solution Service Corporation) Venue: Anna Auditorium |
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| 10:30 AM to 11:00 AM | Invited Talk 2: Quantum Technologies and Chip Design (Dr. S.D.Sudarsan, Executive Director, CDAC, Bangalore) Venue: Anna Auditorium |
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| 11.00 AM to 11.30 AM | Networking Break Venue: CS Hall |
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| 11.30 AM to 1.00 PM | Design Contest Venue: Kamaraj Auditorium |
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| 11.30 AM to 1.00 PM | Technical Session 2 | ||||||||||||||||||||||||||||||||||||||||
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| 1.00 PM to 2.00 PM | Networking Lunch Venue: Anna Auditorium Basketball Court |
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| 2.00 PM to 3.30 PM | Technical Session 3 |
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| 3.30 PM to 4.00 PM | Tea Break Venue: Technology Tower - Gallery 2 |
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| 4:00 PM to 4:30 PM | Awards and Valedictory Venue: Technology Tower - Gallery 2 |
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| 5:00 PM to 7:00 PM | Exploring Vellore |
Hitesh Garg is the Vice President & India Managing Director for NXP Semiconductors and is leading the India Business Operations for all 4 sites – Noida, Bangalore, Hyderabad and Pune.
Hitesh also serves as the R&D Leader for AMS Competence Centre in NXP. In his technical role, he is responsible for building world-class Analog/RF IPs and Sub-systems for NXP Products. His teams in Netherlands and India are busy designing differentiating IPs/Sub-systems/Products in areas of Security and Connectivity, ADAS, In-Vehicle Networking and Smart Car Access.
Hitesh has more than 25 years of experience in Analog Mixed Signal product development. Prior to NXP, Hitesh worked in Conexant Systems, Microchip and state-owned Semiconductor Complex Limited in various technical and lead roles.
Hitesh holds a bachelor’s degree in Electronics & Communication and a Post Graduate Degree in Management from IIM Bangalore.
Sridhar Vembu is the co-founder and CEO of Zoho Corp. He is known for his unconventional choices. Sridhar started a product company in India when the service sector was all the rage in the IT sector. In 2005, he began the Zoho University programme with six high school students, who were trained for two years in computer science and eventually absorbed in the company. Currently, 15% of Zoho's workforce is made of ZU graduates. Instead of opening new offices in metros, he prefers smaller towns or suburbs. In 2016, the Tenkasi office located in rural India launched Zoho Desk, a product that was developed there.
Sridhar Vembu has also been instrumental in deepening and broadening the product portfolio of Zoho, stressing on the need for an integrated suite that solves all business problems end-to-end. He also advocates investing more on R&D than marketing. As a result, in 2017, Zoho launched Zoho One, a revolutionary suite that offered 40+ products at just $30 per employee, per month.
Dr. Satya Gupta is a techno-visionary with 40+ years’ experience in the Global Semiconductor and Electronics Industry. After a 12year corporate career at Intel, he co-founded 4 successful start-ups, Intel Micro-Electronics, Open-Silicon, Concept-2-Silicon and SenZopt.
He co-founded India Semiconductor Association (IESA) in 2005 and was IESA Chairman for years 2012-13 and 2020-2021. He also co-Founded and was founding CEO of EPIC Foundation.
His Vision and Mission is “Make India an Electronics & Semiconductor Product Nation” and take “VLSI Design and semiconductor education” at B. Tech. to 500+ colleges all parts of India and enable every student to do “One Tape-Out before graduation (OTBG)”.
He is currently President of VLSI Society of India and visiting faculty at IIT Roorkee, IIT Gandhinagar and Gati Shakti University.
He has done his education at BITS Pilani, IIT Delhi and Old Dominion University. He holds 6 Global patents and has authored more than 40 Technical Papers.
He is recipient of IEEE Gordon Bell award for the fastest computer in the world and breaking the Tera-Flop barriers for the first time in 1995.
He has also received Lifetime achievement award from VLSI Society of India and Distinguished service award from BIT, Pilani.
Generative AI is taking the world by storm and unleashing the imagination of millions of people with exciting new applications and use cases for individuals and organizations. Enabling these applications need a huge hardware infrastructure, which needs to scale at fast pace, while keeping energy requirements in control. Join me to hear about HW components, scale-up and care-about, to be ready for AI era.
Navin is India Country Manager and AVP Central Engineering at Marvell India. As the India Country Manager, he oversees all business operations, as well as represents the company externally. As an engineering leader, he has led Custom ASIC Design for Infrastructure domain (covering Networking, Processor, Cloud, Automotive and AI/ML applications). Prior to this, he has worked with IBM, Freescale, Cadence, and TI for automotive, consumer and custom ASIC designs. He had received his bachelor's degree in Electronics and Communication from NIT Surathkal.
He has been an active member in EDA standards, Conferences, and Industry associations. He is the Founding member of ITC India and TTTC India, to drive the growth of DFT/Test in India Semiconductor Eco-system and served as General Chair of ITC India for first 5 years. He has contributed as advisory committee for Karnataka state skilling committee and for India Semiconductor Mission R&D eco-system committee. He is also an Executive Council Member of India Electronics and Semiconductor Association.
The aggressive demand for high performance devices in the areas of AI/ML, compute, 5G & datacentres have rapidly driven the pace of semiconductor integration densities. With Moore's law showing signs of slowing down, the need to pack more transistors in a device is no longer met only by technology & process shrinks. Larger dies increase capacity but bring variability and unpredictability in yield. 3D-IC technology provides a solution to this concern by integrating die or chiplets adjacent or stacked vertically. Like any new technology area, 3D integration comes with its own kitty of design and test challenges. This talk will share interesting insights in to some of these challenges and solutions proposed in Industry to circumvent them. The focus of this presentation would be to understand the new techniques & standards to target 3D-IC manufacturing testability and achieve high quality at manageable cost.
Srijesh has over 20 years of experience in Design for Test (DFT), System-on-Chip (SoC) and Hardware Engineering. He is currently leading the Applications Engineering team at Siemens EDA driving industry's best-in-class Silicon Test & Diagnosis solutions with Tessent. As a technologist with extensive experience in handling complex ASIC & Multi-chip SoCs, his passion is to drive highest Quality Test using most innovative solutions in areas of Architecture, Design, Debug & Silicon Diagnosis. Srijesh has a Bachelor degree in Electronics & Communications from Bangalore University.
Increasing performance demands associated with today's advanced technologies has created unprecedented challenges in both DFT and production analytics. This means that when it comes to dealing the sheer volume of silicon data involved in efficient test deployment and device optimization traditional, manual approaches are no longer adequate. This issue is also being exhibited by the emerging engineering talent shortage. The application of Artificial Intelligence (AI) throughout the EDA stack has emerged as a game-changing solution that provides increased test automation and delivers results almost impossible to achieve with manual efforts. This presentation focuses on pioneering AI-driven test and production analytics solutions from Synopsys' Test and Silicon Lifecycle Management (SLM) product families that automatically achieve the best test QoR and time-to-market while enabling the optimization of silicon health and production and operational metrics as part of a unified analytics environment.
Shamitha Rao is Sr. Manager, Solutions Group at Synopsys actively driving customer engagements on Synopsys TestMAX family of products. Prior to joining Synopsys, she was associated with Intel, focusing on end-to-end DFT implementation and validation for complex subsystems and SOCs across different process nodes. She has over 18+ years of experience in DFT with prominent companies like Siemens EDA, STMicroelectronics, Wipro with a broad experience ranging from test architecting to silicon bring up. She has received multiple organizational awards, authored several papers and publications at various conferences like ITC, ATS, ETS etc
Semiconductors are ubiquitous but mostly hidden. They underlie the fabric of our modern lives, powering everything from cell phones to automobiles, washing machines to the largest airplanes. It is difficult to believe that the history of semiconductors spans less than one hundred year. It is equally difficult to believe the complexity that these marvels of technology hide. In this talk we go over this brief history, highlighting the major players. We she some light on the complexity and what makes this complexity possible. Finally, we try to peep into the future to see what it holds
Alok Kuchlous is the Chief Executive Officer and co-founder of Mirafra. Before starting Mirafra, he was a Director of Engineering at Synopsys, responsible for VCS-MX and SystemVerilog solutions. Alok has an MS in Computer Engineering from University of Southern California and a B. Tech. in Electrical Engineering from Indian Institute of Technology, New Delhi. Alok is passionate about learning and teaching. He is known to take random online courses and actually complete them. He has taught students ranging in age from 6 years to 36 years. The subjects have included Python, C/C++, Physics, Recreational Mathematics, Object Oriented Programming and SystemVerilog
Mickael Lozac'h is a business development manager at Yokogawa Solution Service Corp. since April 2023 in the Minimal Fab Business Division. Prior to that, he was a researcher at the National Institute of Advanced Industrial Science and Technology (AIST) in Tsukuba, Japan, since November 2013 mainly in the field of solar energy with expertise in semiconductor processes, optical and electronic characterizations. He got his PhD in 2013 at the University of Tsukuba, Japan, and NIMS on InGaN material growth and characterization for the development of solar energy material.
Nachiket Haridas is the director of RENESAS ELECTRONICS INDIA PRIVATE LIMITED. His leadership and skills in Technology Trends , Customer Requirements , Problem Solving , Cross-team Collaboration , Embedded Devices , Communication ,Budget Management , Delegation , Semiconductor Industry · Customer Experience ,Talent Pipelining led the System Solution Team to excel in crafting solution strategies that resonate with the dynamic market, leveraging insights directly from customer experiences. The establishment of a robust Business Development and Marketing function has empowered us to enhance solution selling, notably reducing time-to-market and total cost of ownership for Renesas customers. He is with Renesas from the last thirteen years and contributed his service in many capacities from Manager to Senior Principle Manager.
Emergence of quantum technology with increasing TRLs is changing the landscape across domains. This talk would focus on chip design specific aspects.
Three decades of R&D as a researcher and manager. Diverse technical and domain experience. Organized professional meetings and seminars at International and National Level. Active with professional bodies including IEEE, ACM, and IETE. Involved in various standards related activities at IEC/ISO/BIS and various committees as well as task forces.
Specialization: Engineering, Analytics, Industrial IoT, Mining, Information Retrieval, Cyber Physical Systems, Cyber Security, Next Generation Networks, Wireless Sensor Networks, R&D Management.
Domains: Safety and mission critical systems; Industry; Infrastructure; Healthcare; Tactical Networks
Chitra Hariharan is a serial entrepreneur & techno-commercial leader coming with rich industry experience with a unique mix of corporate and start-ups in the Electronics & Semiconductor domain. Currently Chitra s heading Start-up collaborations, Academia relations and Govt affairs at Renesas.. She had 2 leadership stints at Intel and successfully built 4 Semiconductor & Electronics product start-ups, being part of the founding team carrying out technical, commercial and operational roles. All the 4 start-ups - Intel Micro Electronics, Open-Silicon, Concept2Silicon and SenZopt had successful exits.
Yadav Preet is Head India Innovation Ecosystem at NXP Semiconductors. Prior to re-joining NXP in his second stint, he was working with Wipro as Analog Practice Head, Distinguished Member of Technical Staff (DMTS) - Wipro Senior Member, leading Analog & Mixed Signal Practice globally in VLSI Technology Group.
He has two decades of enriched R&D experience in the diversified Semiconductor industry. He received B. Tech. in ECE from Kurukshetra University and M. Tech. in VLSI Design & CAD from Thapar Institute of Engineering & Technology.
In past he worked at Semiconductor Complex Ltd. and, Cadence Design Systems. He is Chairperson of IEEE Circuit and Systems Society (CASS), Delhi Chapter, Chair-Elect of IEEE CASS - VLSI Systems & Applications Technical Committee-VSATC, voting member of IEEE CASS Standards Committees-SASD & CASS Industry Engagement Committees. He is Associate Editor of IEEE Sensors Alert.
He received President Award in Scouts & Guides and accoladed with various awards of merit. He has 22 publications in international/national IEEE conferences, with three best paper awards.
He is the youngest Fellow of Indian Society of Systems for Science and Engineering (ISSE), Fellow of The Institution of Electronics Telecommunication Engineers (IETE), & IEEE Senior Member.
Srikanth Puvvada, based in Bengaluru, KA, IN, is currently a Senior Architect, Digital SoC Development in Krutrim. Srikanth Puvvada brings experience from previous roles at Intel, Ericsson, St-Ericsson, Qualcomm and Texas Instruments. Srikanth Puvvada holds a 1999 - 2001 Master of Technology (MTech) in Microelectronics and VLSI @ Indian Institute of Technology, Kanpur. With a robust skill set that includes SoC, ASIC, VLSI, Static Timing Analysis, Verilog and more.
Venkat has over 25+ years of experience in VLSI Industry, with a mix of design, application engineering and Skill Development experience.
He is founder & president of ChipEdge Technologies Pvt Ltd, a VLSI Skill Development company offering skill development programs for last 12 years and produced 5000+ trained VLSI Engineers to semiconductor industry ECO System.
Venkat Co-founded, Celton Semiconductors Pvt Ltd in 2022, which offers Engineering Design Services in VLSI and Embedded Systems.
Prior to founding ChipEdge, he was with Cadence Design Systems (India) Pvt Ltd, Bangalore and was responsible for synthesis solutions. He worked with Time to Market (india) pvt Ltd, Hyderabad and was responsible for Physical Design projects.
Before moving back to india, Venkat was with Cadence Design Systems Inc (SanJose, California) and was responsible for synthesis solutions. He started his career with Qualcore Logic Pvt Ltd, hyderabad and was responsible for FPGA to ASIC migration projects which involved synthesis, STA, DFT, validation, timing simulation & formal verification.
He is a member of Talent Core Initiative Committee(CIG) in IESA (India Electronics & Semiconductor Association) and contributing in Skill Development initiative in ESDM (Electronics System Design & Manufacturing) sector.
Venkat holds a Bachelor’s Degree in ECE from Andhra University.
Dr. V. S. Kanchana Bhaaskaran is the Vice Chancellor of Vellore Institute of Technology (VIT). She obtained her Bachelors in Engineering from the IE(I), Masters from BITS and PhD from Vellore Institute of Technology. With nearly 44 years of experience, Professor Bhaaskaran has served industry, teaching and research.
After 11 years of teaching in SSN College of Engineering, she joined VIT Chennai and had been donning the role of the Dean of Academics. Her areas of specialization include VLSI Design for Low Power, Microprocessor Architectures and Linear Integrated Circuits. She has published around 140 papers in international journals and reputed conferences, and has three patents published in her own field of research. She writes on Higher Education and impact of ICT in learning, and delivers invited lectures. She is the author of 4 books on Linear Integrated Circuits and related subjects published by McGraw Hill Education and has contributed to book chapters on Low Power VLSI Circuit Design.
She is a Fellow of the Institution of Electronics and Telecommunication Engineers (IETE), Fellow of the Institution of Engineers (India) (IEI), Senior Member in IEEE, Member in IET and Life Member of the ISTE.
Ganesh C. Patil received the bachelor’s degree in electronics and telecommunication engineering from the University of Pune, Pune, India, in 2002, the M.Tech. degree from the College of Engineering Pune, Pune, in 2007, and the Ph.D. degree in microelectronics and VLSI from the Indian Institute of Technology Kanpur, India, in 2014.,
He is currently an Associate Professor with the Center for VLSI and Nanotechnology, Visvesvaraya National Institute of Technology, Nagpur, India. His research areas include device physics and modeling, novel nanoscale MOSFETs, and organic electronics. He was a recipient of the Best Student Award at the 4th International Student Workshop on Electrical Engineering at Kyushu University, Fukuoka, Japan. Prof. Patil is a reviewer of various reputed journals and worked as Technical Program Chair for various IEEE international conferences
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