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Three Days National Level Workshop on DESIGN FOR TESTABILITY
Feb 01 - Feb 03

Three Days National Level Workshop on DESIGN FOR TESTABILITY

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Design For Testability (DFT) is a specialisation in the SOC design cycle, which facilitates a design for detecting manufacturing defects. With increase in size & complexity of chips, facilitated by advancement of manufacturing technologies, it has evolved as a specialization in itself over a period of time. DFT Engineers, works on introducing various test structures as part of the design flow, to increase the testability of logic, pads, memories, interconnects. The course is designed and will be delivered by experts in DFT. Importance is given to cover the concepts, methodology thoroughly with good emphasis on hands-on training, using Industry Standard DFT tools with at least 50 % time allocated to lab sessions.