Events

Value Added Programme on VAC2336 RTL to GDSII (SYSTEM ON A CHIP DESIGN)
10-03-2024

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21-04-2024
 Department of Micro & Nano Electronics, SENSE
 TT238, Technology Tower, VIT, Vellore
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With today's increasingly large and complex digital IC and system-on-chip (SoC) designs, design power closure, circuit power integrity and Testing become one of the main engineering challenges, thereby impacting the device's total time-to-market. This Training will teach you how to implement a design from RTL-to-GDSII using various industry standard tools. You will start by coding a design in Verilog, simulate, synthesize and optimize for a better design.

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