It is an engaging three-day program designed to Circuit branch participants in the fundamentals of ASIC design and hardware description languages, particularly Verilog. Starting with an introduction to ASIC design flow, the event progresses through key concepts like combinational and sequential circuit design, FSM implementation, and reusable module creation. With hands-on sessions, participants explore practical RTL coding projects. The bootcamp culminates in group projects, presentations, and feedback.

"The scheduled program has been postponed to July 2025. The exact dates will be announced as soon as possible (ASAP)."