Digital System Design Lab
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Digital System Design Lab
Overview
The Digital System Design Laboratory is a dedicated teaching and research facility for modern digital electronics. It supports courses in Digital System Design and Digital Logic Design, with a strong emphasis on Verilog HDL programming and FPGA‑based implementations. The lab also provides courses on Microcontroller and Embedded programming imparting knowledge on Assembly Language Programming, Embedded C and ARM programming. The lab bridges classroom learning with real‑world practice, enabling students to design, simulate, and prototype digital and embedded systems. In addition to regular academic curriculum, the lab also facilitates organizing various FDP’s, internship programs, workshops etc. on FPGA and Embedded Systems platforms
Objectives
- Provide hands‑on training in Verilog and FPGA platforms.
- Strengthen foundational knowledge in digital logic and system design.
- Enable students to interface microcontrollers with external devices.
- Foster innovation in reconfigurable computing and embedded applications.
Key Focus Areas
- Verilog HDL Programming: Modeling, simulation, and synthesis of digital systems.
- FPGA Development: Prototyping with DE10‑Lite boards.
- Microcontroller Kits: Interfacing with peripherals such as keyboards, LCDs, and other I/O devices.
- Digital Logic Design: Combinational and sequential circuit design.
Major Equipment and tools available
Recent Publications and Patents
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Naman Goyal, Partha Pratim Gogoi, Abhishek N. Tripathi, N.M. Laskar, “Resource-Efficient FPGA Realization of Chess960 Position Generator for Future Covert Communication Systems,” 2025 IEEE 1st International Conference on Smart Inn
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ovations in Systems, Infrastructure, Mechanical, Power, AI and Computing Technologies (SISIMPACT), November 2025
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Sakthi G, Abhishek N. Tripathi, “Systolic Array Design for Efficient FPGA Implementation of CNN Accelerators: Power and Area Optimizations,” Computer Science, Engineering 2025 International Conference on Computational, Communication and Information Technology (ICCCIT), February 2025.
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N.M.Laskar, S.Devi, S.Kumaravel, M.N.Hasan, S.Choudhury, A.Pandey, “ Optimal Design of a Biomedical Amplifier for minimum offset using a modified ABC algorithm,” Solving with Bees: Transformative Applications of Artificial Bee Colony Algorithm, Springer, pp.117-132, 2024.
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J.B.Yogeshwar, N.M.Laskar, A.Samuel, A.Solomon, V.Vijayvargiya, “Design and Analysis of Low Noise, Low Power OTA considering design trade-offs for Biomedical Applications,” Results in Engineering, Elsevier, vol.26, pp.105013, June, 2025.
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S Devi, NM Laskar, S Nirgude, S Srivastava, “ Optimizing Circuit Synthesis: Integrating Neural Networks and Evolutionary Algorithms for Increased Design Efficiency,” Advancing VLSI Through Machine Learning, CRC Press, pp.1-13, 2025.
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B.Raathore, Shreyashi, N.M.Laskar, A.N.Tripathi, A.Pandey, S.Mago, “Non-Invasive Smart Helmet System with Integrated Biometric Fatigue Detection,” Indian Patent Application No. 202541093702, Indian Patent Office, June 13, 2025 (Published)
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S.E.Karthikeyan, N.M.Laskar, T.Ghatte, K.Kashyap, V.Vijayvargiya, “ Real-Time Gesture Recognition Glove for Sign-to-Speech Translation,” Indian Patent Application No. 202541052665, Indian Patent Office, June 13, 2025 (Published)
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R.Parthipan, N.M.Laskar, Raajaprasanna M, V.Vijayvargiya, Vigneshwaran V, Lakshmanan R, “Gesture-Based Wearable Wheelchair Control System,” Indian Patent Application No. 202541061821, Indian Patent Office, July 11, 2025 (Published)
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A.S.Rassel, N.M.Laskar, A.N.Tripathi, S.Singh, V.Vijayvargiya, “Smart Helmet with Cloud-Based Safety Alerts,” Indian Patent Application No. 202541040824, Indian Patent Office, May 23, 2025 (Published)
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M.Gandhi, F.Hana, N.M.Laskar, V.Vijayvargiya, “ System and Method for Air Quality Monitoring And Forecasting,” Indian Patent Application No. 202641022149, Indian Patent Office, March, 2026 (Published)
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R.Divesh, K.Y.Reddy, H.Muraledharan, M.P.Golkondda, N.M.Laskar, A.N.Tripathi, “ System and Method for Vehicle Safety Monitoring and Accident Prevention,” Indian Patent Application No. 202641022153, Indian Patent Office, March, 2026 (Published)
- SJT 203
- Current Lab In-Charge: Dr. Naushad Manzoor Laskar
- Lab Technician: Mr. Kathirvelu N
