The ASIC Design workshop primarily focuses on providing comprehensive hands-on experience in ASIC design and physical verification using Synopsys EDA tools and extensive lab practice. By the end of the course, participants will have a thorough understanding of the complete ASIC design flow, which includes synthesis, partitioning, floor planning, power planning, timing analysis, clock tree synthesis, and routing of functional unit blocks, as well as physical verification and sign-off checks. This workshop also assists faculty in guiding students as they work towards chip design for fabrication.