Events

Two Day Training on Semiconductor Circuit Design and Simulation
10-01-2026

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11-01-2026

TOPICS TO BE COVERED

  • CMOS Logic Simulation Using Cadence Virtuoso
  • Hands-On Different Logic Simulation - CMOS
  • Parametric Analysis, Power estimation - Cadence Virtuoso
  • Delay Estimation & Performance Metrics - Cadence Virtuoso
  • Introduction to Verilog HDL
  • RTL Simulation and Synthesis Using Cadence tools (Nclaunch + genus)
  • Placement and CTS Using Cadence Innovus
  • Complete Physical design using cadence Innovus

Value Added Programme on Public Speaking – (VAC2363) Speak to Succeed: From Everyday Talk to Formal Stages
VIT Synergy 2026
FOOD SAFETY SUPERVISOR (FSS) TRAINING
National Workshop on Digital Signal Processing: AI and Computing Perspective (Online Mode)

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