Events

Value Added Course on VAC2336 RTL to GDSII (SYSTEM ON A CHIP DESIGN)
07-02-2026

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04-04-2026

With today's increasingly large and complex digital IC and system-on-chip (SoC) designs, design power closure, circuit power integrity and Testing become one of the main engineering challenges, thereby impacting the device's total time-to-market. This VAC will teach you how to implement a design from RTL-to-GDSII using various industry standard tools. You will start by coding a design in Verilog, simulate, synthesize, optimize and PnR for a better design.

Cyber Forensics for VIT 36 Hours Hackathon
One day International Workshop on the Art of Manuscript Writing and Successful Publication
Industry- Academia Conclave on “Bridging Innovation: Shaping Tomorrow’s Technology”
Value-Added Course on VLSI Design using CADENCE Tools (VAC 1555)

Beware of VITEEE fake websites

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